1. Field of the Invention
This invention relates to integrated circuit design and, more particularly, to electronic design automation tools providing integrated circuit custom block composition.
2. Description of the Related Art
During the integrated circuit (IC) design process the logic designers typically create the various circuits using a hardware definition language such as Verilog or very high speed IC hardware description language (VHDL). In these and similar languages, the operation of synchronous digital circuits may be described using a register transfer level (RTL) description. Typically the RTL describes the circuit's behavior in terms of the signal flow (or data transfer) through hardware registers and combinatorial logic. The RTL may be synthesized into a gate level description or netlist using a synthesis tool. The output of the synthesis tool may be used by a place and route tool to generate a physical layout of the IC. The physical layout represents the physical locations of each transistor and the wiring and interconnections to those transistors. The physical layout output may include a file such as a GDSII file, for example, which may be used to create a mask set for use in the actual manufacturing process of the IC.
The place and route tool creates the physical layout from the netlist and a library of components that make up the IC. For example, the library may include a vast number of standard cells that may be used in many different ICs. A typical standard cell library may include a variety of commonly used and basic circuit gates and components such as AND, NAND, OR, and NOR gates, for example, as well as inverters, flip-flops, and the like. In some cases, the standard cell library may already exist from other IC designs that used that facility and technology. These standard library cells include information that corresponds to the transistor drive strength, the characteristics of the given transistors for a given process, and the like. Standard library cells are typically the same size such that when a standard block is created the standard cells in a row are all the same width.
Custom cells or leafcells, on the other hand are non-standard cells that define a special function such as, for example a decoder for a memory block. Custom cells may include some standard library cells. A custom block may be a large block created from both standard library cells and custom cells. A custom block may represent a larger function. In the example above, the custom block may be the entire memory block.
During the placement operation of the IC design, the cells and blocks may be physically placed into an IC floorplan and the route portion connects everything together by routing the wires. The place and route tool uses a number of rules to determine where to place the components. For example, total wire length, timing of the longest delay paths, congestion, and power minimization, may be taken into account. The routing portion includes figuring out how to connect all the components and creating all the wires to do it.
Conventional automated place and route tools do a relatively good job of producing circuit block designs that meet timing when the cells within the blocks are chosen from standard library cells. However, when custom blocks are created using non-standard library cells, in many cases, the conventional automated place and route tools may have a difficult time, at best, placing non-standard-width custom leafcells and meeting timing. In such cases, a person such as a mask designer will have to go back into the design and manually place leafcells and re-route many wires. This can be a tedious task that can take a long time, thereby adding time to the design cycle, which may directly translate to lost opportunities and lost dollars.